There is a general need for materials with low dielectric constants (low-k) in the integrated circuit manufacturing industry. Using low-k materials as the interlayer dielectric of conductive interconnects reduces the delay in signal propagation and signal crosstalk due to capacitive effects. Further, the use of low k materials as interlayer dielectrics reduces power consumption of complex integrated circuits.
Low-k dielectrics are conventionally defined as those materials that have a dielectric constant (k) lower than that of silicon dioxide (SiO2), that is k<˜4. Generally, they have a dielectric constant of 3.2 or less. Typical methods of obtaining low-k materials include introducing pores into the dielectric matrix and/or doping silicon dioxide with various hydrocarbons or fluorine. In technology nodes of 90 nanometers and beyond, carbon doped oxide dielectric materials look extremely promising. However, wide spread deployment of these materials in modern integrated circuit fabrication processes presents some technological hurdles.
Specifically, in comparison with silicon dioxide, low k CDO materials typically have inferior mechanical properties due to the incorporation of ending methyl groups (—CH3) in order to lower the k value of CDO materials. These mechanical properties include hardness, modulus, film residual stress, blanket film cracking threshold or limit, fracture toughness, etc. These properties are derived primarily from the strength of the atomic bonds and their binding energy. For instance, when using conventional Si containing organics as precursors in a conventional plasma enhanced chemical vapor deposition (PECVD) process, the resulting dielectric CDO film will usually possess a dielectric constant of 2.7-2.95 with a hardness of 1.2-2.0 GPa, modulus of 6.6 to 12 GPa, and a blanket film cracking limit between 2.3-2.7 μm. It is noted that the cracking limit is an overall measure of mechanical properties of a CDO film. Many applications will require cracking thresholds of greater than 3 μm, and more preferably greater than 5 μm. CDO materials of inferior mechanical properties will have adhesive (delamination) and cohesive (cracking) failures during the Cu-low k integration and packaging steps. These failures are exacerbated by the increasing complexity of integrated circuits and manifest as growing numbers of metallization layers. It is not uncommon for a modern IC design to require nine metallization layers, each with a separate dielectric layer. Each of these dielectric layers will have to withstand mechanical stresses from, for example, Chemical Mechanical Polishing (CMP) and/or thermal and mechanical stresses incurred during IC packaging operations.
In addition to modulus, a mechanical property of growing importance is the residual (or internal) stress in a dielectric film. As explained below, residual stress is comprised of an extrinsic stress component and an intrinsic stress component. Further, residual stress can be either compressive or tensile. Conventional low k films (k<3.2), including CDO films, typically have a tensile stress in excess of 50 MPa. The residual stresses within a deposited dielectric film are of particular interest for this invention. In IC fabrication contexts, these stresses can manifest in different ways, including cracking initiation and propagation and bowing or arching of die, which indicate net tensile or compressive stress. Low residual stress leads to a low cracking driving force, a high cracking or buckling limit and hence a low failure rate during Cu-low k integration and packaging.
Many device failures can ultimately be traced to stresses and their variations at various stages of IC processing. Those failures include interfacial delamination between different materials and cracking within one material during chemical mechanical polishing (CMP) and packaging. Excessive stress of thin films, such as CDO films, will also accumulate through multiple layer integration and will result in wafer warping and CMP issues. Since device feature size is continuously shrinking, stress related problems are expected to become more severe.
Thus, there is a need for low-stress dielectric films. However, methods that create lower stress CDO films often produce films with significantly different chemical properties than the CDO films in use in many current applications. Generally, the suitability of a low dielectric constant film can be determined by the ease with which it can be integrated into an interconnect stack. Ideally, it is desirable that low-stress films have comparable etch rates when compared with existing low-k material layers. Some current methods of creating low-stress CDO films result in low-k films with refractive indices/etch rates which are very similar to oxygen doped carbide materials which are often used as barrier layers, resulting in comparable etch rates for barrier layers and low-k material layers-potentially complicating integration and creating a need for new integration schemes. Thus, there is a high demand for methods that will produce low-stress, low-k CDO films with refractive indices/etch rates similar to existing conventional low-k films.
To achieve the foregoing, methods of improving the mechanical properties of thin films, including CDO films, are disclosed. Further, this invention relates to techniques for creating low-stress, low-k carbon-doped oxide (CDO) layers by modifying the CDO film's structure using chemical bond reconstruction to alter SiC/SiO ratios such that the refractive index/etch rate of the CDO material is similar to that of existing conventional low-k films. In particular, this invention presents methods to modify the film structure of a low-stress CDO film without an appreciable loss in film performance, thus allowing easier integration of low-stress CDO films into an interconnect stack.
In one embodiment of the invention, a carbon doped silicon oxide (CDO) film is deposited on a substrate by contacting the substrate with one or more CDO precursors having a high carbon content to form a CDO film with a SiC:SiOx bond ratio of not greater than about 0.75, a net tensile stress of less than about 40 MPa, a hardness of at least about 1 GPa, and a dielectric constant of less than about 3.2.
In some embodiments, the CDO film is formed on the substrate by a chemical deposition process (for example PECVD), using one or more precursors carried in a carrier gas such as CO2, Ar, or He. In a specific implementation, the CDO precursor is Ethynyltrimethylsilane (ETMS), also known as trimethylsilaneacetylene (TMSA).
In other embodiments, a secondary precursor is added. In one implementation diethoxymethylsilane (DEMS) and/or tetramethylcyclotetrasiloxane (TMCTS) are added. Further, in one or more of these embodiments, another reactant, hexafluoroethane (C2F6), is introduced into the deposition chamber.
Flow rates of the various precursors, carrier gases, and reactants vary broadly. A typical flow rate for TMSA is the range of between about 0.3 mL/min to 10 mL/min, preferably in the range of between about 2.5 mL/min to 3.5 mL/min. If DEMS is added, the flow rates range broadly from between about 0.3 mL/min to 5 mL/min for each and more preferably in the range of between about 1.5 mL/min to 2.5 mL/min for each. If TMCTS is added, the flow rates range broadly from 1 mL/min to 3 mL/min and more preferably in the range of 1 mL/min to 2 mL/min. The flow rate of O2 ranges broadly between about 100 mL/min to 1000 mL/min, more preferably in the range of 100 mL/min to 400 mL/min. The flow rate for hexafluoroethane varies between about 0 mL/min to 1000 mL/min, preferably between about 0 mL/min to 500 mL/min.
The flow rates of the various carrier gases range broadly as well. For CO2, the broad range is between about 1000 sccm to 15000 sccm, while the preferred range is between about 1500 sccm to 8000 sccm. In some embodiments, Ar and He are substituted for CO2. When Ar and/or He are added, flow rates range broadly from between about 1000 sccm to 10000 sccm for each and, more preferably, between about 1500 sccm to 2500 sccm for He and 1500 sccm to 3500 sccm for Ar. In embodiments where Ar and/or He are added, He and Ar flow rates may be the same or different.
In another embodiment of the invention, an integrated circuit (IC) with one or more CDO dielectric layers having carbon-carbon triple bonds or both and/or their derivative forms generated during the deposition is provided. In some embodiments, the CDO layer serves as an interlayer dielectric in the IC. In a preferred embodiment, the CDO dielectric layer has a dielectric constant of less than about 3.2, a net tensile stress of less than about 40 MPa, a hardness of at least about 1 GPa, and a SiC:SiOx bond ratio of not greater than about 0.75.
In still another embodiment, deposited CDO films have a SiC:SiOx bond ratio of between about 0.2 to 0.7, a SiH/SiOx bond ratio of between about 0.01 to 0.18, and a refractive index (RI) of 1.4-1.65 measured at 633 nm.
These and other features and advantages of the invention will be presented in more detail below with reference to the associated drawings.